1. Field of the Invention
The present invention relates to a multiple-input-multiple-output (MIMO) receiver block and in particular to a coordinated automatic gain control (AGC) for such a MIMO receiver block.
2. Related Art
Multiple-input-multiple-output (MIMO) wireless LAN architectures can provide improved performance when compared to single-input-single output architectures. This improved performance may be provided by, in part, using two or more receivers to receive transmitted data.
A typical receiver block for MIMO systems uses multiple input receivers (also called receive chains). FIG. 1 is a block diagram of a prior art MIMO receiver block 100 that includes a first receive chain 110A and a second receive chain 110B. Note that other prior art embodiments may include more than two receive chains.
In this embodiment, first receive chain 110A includes an antenna 101A, an analog front end (AFE) 102A, an analog to digital converter (ADC) 103A, an automatic gain controller (AGC) 104A, and a digital signal processing (DSP) block 106A within a DSP unit 105. Transmitted data in the form of an RF signal is received by antenna 101A and is processed within AFE 102A. Specifically, the RF signal is transformed into a baseband analog signal within AFE 102A. To provide this processing, AFE 102A may include one or more variable gain amplifiers (VGAs) (e.g. a VGA 107A).
AFE 102A provides the transformed RF signal, i.e. the baseband analog signal, to ADC 103A. In turn, ADC 103A converts this baseband analog signal into a digital signal. ADC 103A provides this digital signal to DSP block 106A of DSP unit 105. DSP block 106A may perform further signal processing upon the digital signal to, for example, demodulate or improve the signal quality of the received signal. In some embodiments, DSP unit 105 can use information from more than one DSP block, which is described in greater detail below.
Note that the digital signal generated by ADC 103A is also provided to AGC 104A. AGC 104A can monitor the output of ADC 103A and change the gain of VGA 107A within AFE 102A. The gain of VGA 107A may be changed, for example, to maximize the signal to noise ratio (SNR) of the received signal. For example, if the processed signal produced by AFE 102A is too large, then ADC 103A may saturate and cause distortion of the received signal. In this example, AGC 104A would detect this condition and reduce the gain of AFE 102A using VGA 107A. On the other hand, if the processed signal produced by AFE 102A is too small, then the circuit noise of AFE 102A and ADC 103A may significantly degrade the received signal. In this example, AGC 104A would detect this condition and increase the gain of AFE 102A using VGA 107A. AGC 104A may also change the gain of VGA 107A during the training sequences that are transmitted along with the transmitted data as outlined by, for example, the IEEE 802.11a, 802.11g, or (draft) 802.11n standards. Note that the components of second receive chain 110B are generally similar to those of first receive chain 110A in structure and operation (e.g. AGC 104A is substantially the same as AGC 1048).
As shown in FIG. 1, although second receive chain 110B may be substantially independent of first receive chain 110A, there may be one or more structures common to receive chains 110A/110B within receiver block 100, e.g. DSP unit 105. DSP unit 105 may use information from DSP blocks 106A and 106B to improve demodulation or other aspects of the signal processing of the signals within receive chains 110A and 110B.
The output data of a receive chain may become invalid (i.e. produce invalid data) when the setting of a VGA within an AFE is changed. Typically, a gain change within the AFE needs time to propagate and the processing elements of the receive chain need time to react to the gain change and to settle. This propagation and settling period is often referred to more generically as settling time. Because the operation of the processing elements may be changing during the settling time, the data produced by the receive chain may be uncertain (i.e. the data produced is invalid data). Therefore, after the gain is changed in an AFE, the ADC outputs may be invalid until the settling time has past. If the data produced by the one or more receive chains is invalid, the MIMO (i.e. the combined) data is said to be unaligned.
One advantage of a MIMO receiver block (e.g. receiver block 100) is that the output data from the two or more receive chains may be combined and used to increase the overall performance of the receiver block. In some cases, the data combining process requires that the receive chains produce aligned MIMO data (i.e. produce valid data at substantially the same time). Conversely, if one or more of the receive chains within the receiver block produces invalid data, the data combining process may fail and the overall performance of the receiver block may be impaired.
FIG. 2 is a graph illustrating an example of the output data timing relationship between receive chains 110A and 110B of receiver block 100 (FIG. 1). The top line of data in the graph illustrates the timing of the output data from receive (Rx) chain 110A and the middle line of data in the graph illustrates the timing of the output data from Rx chain 110B. As shown, at time t=t0, Rx chain 110A is producing valid data. For this example, assume that AGC 104A determines that a gain change greater than some threshold should be applied to VGA 107A and thus changes the gain of VGA 107A at time t=t1. This gain change causes the output data of Rx chain 110A to become invalid beginning at time t=t2. The invalid data is typically produced for a period as long as the settling time of AFE 102A. After the settling time of AFE 102A, the output data of Rx chain 110A is again valid as shown in FIG. 2 at time t=t3.
Because receive chains 110A and 110B operate independently, AGC 104B of Rx chain 110B may change the gain of VGA 107B independently of gain changes applied to VGA 107A. Returning to the example, at time t=tv assume that Rx chain 110B produces valid data as shown in FIG. 2. At time t=t8, AGC 104B changes the gain of VGA 107B and the output data of Rx chain 110B may be invalid beginning at time t=t8. The invalid data may be produced for a period as long as the settling time of AFE 102B. After the settling time of AFE 102B, the output of Rx chain 110B is again valid as shown in FIG. 2 at time t=t7.
Because AGCs 104A and 104B can operate independently, the MIMO data produced by combining data from receive (Rx) chains 110A and 1103 can become unaligned. One such period 201 is shown in the bottom line of data in the graph of FIG. 2. Other periods of unaligned MIMO data exist within FIG. 2 (for example, including those periods where both receiver chains produce invalid data), but are not annotated for clarity. As previously described, unaligned MIMO data can undesirably reduce receiver block performance.
Contrasting with unaligned data, periods of aligned data exist when the outputs of the receive chains within the receiver block produce valid data at approximately the same time. Stated another way, aligned MIMO data may be considered to be the logical AND of valid data from the receive chains. For example, referring to the bottom line of the graph in FIG. 2, the time period between t=t, through t=t8 illustrates a period 202 of aligned MIMO data. Other periods of aligned MIMO data are also shown on FIG. 2, but have not been annotated for clarity.
Another method that may be used to set the gains of the receive chains is based on the AGC setting of a single chain. This method assumes that the gain settings for all receive chains in the receiver block are similar. Therefore, the same gain setting may be applied to all VGAs within all the receive chains. Because the same gain setting is applied to all of the VGAs, the AGC controller only needs to determine a single gain setting and cause all of the AGCs to change their respective gains contemporaneously.
While this method may address the problem of unaligned data, the method may provide sub-optimal performance of the receiver block. It is often the case that the signal strength of the received signals may vary substantially from receive chain to receive chain. For example, it is not uncommon for the signal strength to differ by more than 10 dB between two receive chains. Therefore setting the gain of the VGAs to similar levels may provide optimal gain for one particular receive chain, but provide too much or too little gain for other receive chains.
As the foregoing illustrates, there is a need to provide per-chain automatic gain control in a MIMO receiver block while coordinating gain adjustments to maximize aligned data.